
point:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400480 <_init>:
  400480:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400484:	910003fd 	mov	x29, sp
  400488:	94000030 	bl	400548 <call_weak_fn>
  40048c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400490:	d65f03c0 	ret

Disassembly of section .plt:

00000000004004a0 <.plt>:
  4004a0:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  4004a4:	90000090 	adrp	x16, 410000 <__FRAME_END__+0xf2e0>
  4004a8:	f947fe11 	ldr	x17, [x16, #4088]
  4004ac:	913fe210 	add	x16, x16, #0xff8
  4004b0:	d61f0220 	br	x17
  4004b4:	d503201f 	nop
  4004b8:	d503201f 	nop
  4004bc:	d503201f 	nop

00000000004004c0 <__libc_start_main@plt>:
  4004c0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4004c4:	f9400211 	ldr	x17, [x16]
  4004c8:	91000210 	add	x16, x16, #0x0
  4004cc:	d61f0220 	br	x17

00000000004004d0 <__gmon_start__@plt>:
  4004d0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4004d4:	f9400611 	ldr	x17, [x16, #8]
  4004d8:	91002210 	add	x16, x16, #0x8
  4004dc:	d61f0220 	br	x17

00000000004004e0 <abort@plt>:
  4004e0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4004e4:	f9400a11 	ldr	x17, [x16, #16]
  4004e8:	91004210 	add	x16, x16, #0x10
  4004ec:	d61f0220 	br	x17

00000000004004f0 <printf@plt>:
  4004f0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4004f4:	f9400e11 	ldr	x17, [x16, #24]
  4004f8:	91006210 	add	x16, x16, #0x18
  4004fc:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400500 <_start>:
  400500:	d280001d 	mov	x29, #0x0                   	// #0
  400504:	d280001e 	mov	x30, #0x0                   	// #0
  400508:	aa0003e5 	mov	x5, x0
  40050c:	f94003e1 	ldr	x1, [sp]
  400510:	910023e2 	add	x2, sp, #0x8
  400514:	910003e6 	mov	x6, sp
  400518:	580000c0 	ldr	x0, 400530 <_start+0x30>
  40051c:	580000e3 	ldr	x3, 400538 <_start+0x38>
  400520:	58000104 	ldr	x4, 400540 <_start+0x40>
  400524:	97ffffe7 	bl	4004c0 <__libc_start_main@plt>
  400528:	97ffffee 	bl	4004e0 <abort@plt>
  40052c:	00000000 	.inst	0x00000000 ; undefined
  400530:	00400768 	.word	0x00400768
  400534:	00000000 	.word	0x00000000
  400538:	00400bb8 	.word	0x00400bb8
  40053c:	00000000 	.word	0x00000000
  400540:	00400c38 	.word	0x00400c38
  400544:	00000000 	.word	0x00000000

0000000000400548 <call_weak_fn>:
  400548:	90000080 	adrp	x0, 410000 <__FRAME_END__+0xf2e0>
  40054c:	f947f000 	ldr	x0, [x0, #4064]
  400550:	b4000040 	cbz	x0, 400558 <call_weak_fn+0x10>
  400554:	17ffffdf 	b	4004d0 <__gmon_start__@plt>
  400558:	d65f03c0 	ret
  40055c:	00000000 	.inst	0x00000000 ; undefined

0000000000400560 <deregister_tm_clones>:
  400560:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  400564:	9100c000 	add	x0, x0, #0x30
  400568:	b0000081 	adrp	x1, 411000 <__libc_start_main@GLIBC_2.17>
  40056c:	9100c021 	add	x1, x1, #0x30
  400570:	eb00003f 	cmp	x1, x0
  400574:	540000a0 	b.eq	400588 <deregister_tm_clones+0x28>  // b.none
  400578:	90000001 	adrp	x1, 400000 <_init-0x480>
  40057c:	f9462c21 	ldr	x1, [x1, #3160]
  400580:	b4000041 	cbz	x1, 400588 <deregister_tm_clones+0x28>
  400584:	d61f0020 	br	x1
  400588:	d65f03c0 	ret
  40058c:	d503201f 	nop

0000000000400590 <register_tm_clones>:
  400590:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  400594:	9100c000 	add	x0, x0, #0x30
  400598:	b0000081 	adrp	x1, 411000 <__libc_start_main@GLIBC_2.17>
  40059c:	9100c021 	add	x1, x1, #0x30
  4005a0:	cb000021 	sub	x1, x1, x0
  4005a4:	9343fc21 	asr	x1, x1, #3
  4005a8:	8b41fc21 	add	x1, x1, x1, lsr #63
  4005ac:	9341fc21 	asr	x1, x1, #1
  4005b0:	b40000a1 	cbz	x1, 4005c4 <register_tm_clones+0x34>
  4005b4:	90000002 	adrp	x2, 400000 <_init-0x480>
  4005b8:	f9463042 	ldr	x2, [x2, #3168]
  4005bc:	b4000042 	cbz	x2, 4005c4 <register_tm_clones+0x34>
  4005c0:	d61f0040 	br	x2
  4005c4:	d65f03c0 	ret

00000000004005c8 <__do_global_dtors_aux>:
  4005c8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4005cc:	910003fd 	mov	x29, sp
  4005d0:	f9000bf3 	str	x19, [sp, #16]
  4005d4:	b0000093 	adrp	x19, 411000 <__libc_start_main@GLIBC_2.17>
  4005d8:	3940c260 	ldrb	w0, [x19, #48]
  4005dc:	35000080 	cbnz	w0, 4005ec <__do_global_dtors_aux+0x24>
  4005e0:	97ffffe0 	bl	400560 <deregister_tm_clones>
  4005e4:	52800020 	mov	w0, #0x1                   	// #1
  4005e8:	3900c260 	strb	w0, [x19, #48]
  4005ec:	f9400bf3 	ldr	x19, [sp, #16]
  4005f0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4005f4:	d65f03c0 	ret

00000000004005f8 <frame_dummy>:
  4005f8:	17ffffe6 	b	400590 <register_tm_clones>

00000000004005fc <point>:
  4005fc:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400600:	910003fd 	mov	x29, sp
  400604:	52800c80 	mov	w0, #0x64                  	// #100
  400608:	b90023a0 	str	w0, [x29, #32]
  40060c:	52801900 	mov	w0, #0xc8                  	// #200
  400610:	b90027a0 	str	w0, [x29, #36]
  400614:	52802580 	mov	w0, #0x12c                 	// #300
  400618:	b9001ba0 	str	w0, [x29, #24]
  40061c:	52803200 	mov	w0, #0x190                 	// #400
  400620:	b9001fa0 	str	w0, [x29, #28]
  400624:	910083a0 	add	x0, x29, #0x20
  400628:	f9001fa0 	str	x0, [x29, #56]
  40062c:	f9401fa0 	ldr	x0, [x29, #56]
  400630:	f9001ba0 	str	x0, [x29, #48]
  400634:	910063a0 	add	x0, x29, #0x18
  400638:	f90017a0 	str	x0, [x29, #40]
  40063c:	f9401ba0 	ldr	x0, [x29, #48]
  400640:	b9400001 	ldr	w1, [x0]
  400644:	f9401fa0 	ldr	x0, [x29, #56]
  400648:	b9400002 	ldr	w2, [x0]
  40064c:	f94017a0 	ldr	x0, [x29, #40]
  400650:	b9400003 	ldr	w3, [x0]
  400654:	90000000 	adrp	x0, 400000 <_init-0x480>
  400658:	9131a000 	add	x0, x0, #0xc68
  40065c:	97ffffa5 	bl	4004f0 <printf@plt>
  400660:	f9401ba0 	ldr	x0, [x29, #48]
  400664:	91001001 	add	x1, x0, #0x4
  400668:	f9001ba1 	str	x1, [x29, #48]
  40066c:	b9400005 	ldr	w5, [x0]
  400670:	f9401fa0 	ldr	x0, [x29, #56]
  400674:	91001000 	add	x0, x0, #0x4
  400678:	f9001fa0 	str	x0, [x29, #56]
  40067c:	f9401fa0 	ldr	x0, [x29, #56]
  400680:	b9400006 	ldr	w6, [x0]
  400684:	f94017a0 	ldr	x0, [x29, #40]
  400688:	b9400000 	ldr	w0, [x0]
  40068c:	11000402 	add	w2, w0, #0x1
  400690:	f94017a1 	ldr	x1, [x29, #40]
  400694:	b9000022 	str	w2, [x1]
  400698:	90000001 	adrp	x1, 400000 <_init-0x480>
  40069c:	91324024 	add	x4, x1, #0xc90
  4006a0:	2a0003e3 	mov	w3, w0
  4006a4:	2a0603e2 	mov	w2, w6
  4006a8:	2a0503e1 	mov	w1, w5
  4006ac:	aa0403e0 	mov	x0, x4
  4006b0:	97ffff90 	bl	4004f0 <printf@plt>
  4006b4:	f9401ba0 	ldr	x0, [x29, #48]
  4006b8:	b9400001 	ldr	w1, [x0]
  4006bc:	f9401fa0 	ldr	x0, [x29, #56]
  4006c0:	b9400002 	ldr	w2, [x0]
  4006c4:	f94017a0 	ldr	x0, [x29, #40]
  4006c8:	b9400003 	ldr	w3, [x0]
  4006cc:	90000000 	adrp	x0, 400000 <_init-0x480>
  4006d0:	9131a000 	add	x0, x0, #0xc68
  4006d4:	97ffff87 	bl	4004f0 <printf@plt>
  4006d8:	d503201f 	nop
  4006dc:	a8c47bfd 	ldp	x29, x30, [sp], #64
  4006e0:	d65f03c0 	ret

00000000004006e4 <modify_array>:
  4006e4:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4006e8:	910003fd 	mov	x29, sp
  4006ec:	52800c80 	mov	w0, #0x64                  	// #100
  4006f0:	b9001ba0 	str	w0, [x29, #24]
  4006f4:	52801900 	mov	w0, #0xc8                  	// #200
  4006f8:	b9001fa0 	str	w0, [x29, #28]
  4006fc:	910063a0 	add	x0, x29, #0x18
  400700:	f90013a0 	str	x0, [x29, #32]
  400704:	f94013a0 	ldr	x0, [x29, #32]
  400708:	52800cc1 	mov	w1, #0x66                  	// #102
  40070c:	b9000001 	str	w1, [x0]
  400710:	b9002fbf 	str	wzr, [x29, #44]
  400714:	1400000d 	b	400748 <modify_array+0x64>
  400718:	b9802fa0 	ldrsw	x0, [x29, #44]
  40071c:	d37ef400 	lsl	x0, x0, #2
  400720:	910063a1 	add	x1, x29, #0x18
  400724:	b8606821 	ldr	w1, [x1, x0]
  400728:	90000000 	adrp	x0, 400000 <_init-0x480>
  40072c:	91330000 	add	x0, x0, #0xcc0
  400730:	2a0103e2 	mov	w2, w1
  400734:	b9402fa1 	ldr	w1, [x29, #44]
  400738:	97ffff6e 	bl	4004f0 <printf@plt>
  40073c:	b9402fa0 	ldr	w0, [x29, #44]
  400740:	11000400 	add	w0, w0, #0x1
  400744:	b9002fa0 	str	w0, [x29, #44]
  400748:	b9402fa0 	ldr	w0, [x29, #44]
  40074c:	7100041f 	cmp	w0, #0x1
  400750:	54fffe4d 	b.le	400718 <modify_array+0x34>
  400754:	d503201f 	nop
  400758:	a8c37bfd 	ldp	x29, x30, [sp], #48
  40075c:	d65f03c0 	ret

0000000000400760 <double_point>:
  400760:	d503201f 	nop
  400764:	d65f03c0 	ret

0000000000400768 <main>:
  400768:	a9aa7bfd 	stp	x29, x30, [sp, #-352]!
  40076c:	910003fd 	mov	x29, sp
  400770:	a9137fbf 	stp	xzr, xzr, [x29, #304]
  400774:	a9147fbf 	stp	xzr, xzr, [x29, #320]
  400778:	f900abbf 	str	xzr, [x29, #336]
  40077c:	52800140 	mov	w0, #0xa                   	// #10
  400780:	b90133a0 	str	w0, [x29, #304]
  400784:	528001e0 	mov	w0, #0xf                   	// #15
  400788:	b90137a0 	str	w0, [x29, #308]
  40078c:	52800280 	mov	w0, #0x14                  	// #20
  400790:	b9013ba0 	str	w0, [x29, #312]
  400794:	52800320 	mov	w0, #0x19                  	// #25
  400798:	b9013fa0 	str	w0, [x29, #316]
  40079c:	528003c0 	mov	w0, #0x1e                  	// #30
  4007a0:	b90143a0 	str	w0, [x29, #320]
  4007a4:	52800500 	mov	w0, #0x28                  	// #40
  4007a8:	b90147a0 	str	w0, [x29, #324]
  4007ac:	910803a0 	add	x0, x29, #0x200
  4007b0:	a930fc1f 	stp	xzr, xzr, [x0, #-248]
  4007b4:	910803a0 	add	x0, x29, #0x200
  4007b8:	a931fc1f 	stp	xzr, xzr, [x0, #-232]
  4007bc:	f90097bf 	str	xzr, [x29, #296]
  4007c0:	52800140 	mov	w0, #0xa                   	// #10
  4007c4:	b9010ba0 	str	w0, [x29, #264]
  4007c8:	528001e0 	mov	w0, #0xf                   	// #15
  4007cc:	b9010fa0 	str	w0, [x29, #268]
  4007d0:	52800280 	mov	w0, #0x14                  	// #20
  4007d4:	b90113a0 	str	w0, [x29, #272]
  4007d8:	52800320 	mov	w0, #0x19                  	// #25
  4007dc:	b90117a0 	str	w0, [x29, #276]
  4007e0:	528003c0 	mov	w0, #0x1e                  	// #30
  4007e4:	b9011ba0 	str	w0, [x29, #280]
  4007e8:	52800500 	mov	w0, #0x28                  	// #40
  4007ec:	b9011fa0 	str	w0, [x29, #284]
  4007f0:	a90e7fbf 	stp	xzr, xzr, [x29, #224]
  4007f4:	a90f7fbf 	stp	xzr, xzr, [x29, #240]
  4007f8:	f90083bf 	str	xzr, [x29, #256]
  4007fc:	52800140 	mov	w0, #0xa                   	// #10
  400800:	b900e3a0 	str	w0, [x29, #224]
  400804:	528001e0 	mov	w0, #0xf                   	// #15
  400808:	b900e7a0 	str	w0, [x29, #228]
  40080c:	52800280 	mov	w0, #0x14                  	// #20
  400810:	b900eba0 	str	w0, [x29, #232]
  400814:	52800320 	mov	w0, #0x19                  	// #25
  400818:	b900efa0 	str	w0, [x29, #236]
  40081c:	528003c0 	mov	w0, #0x1e                  	// #30
  400820:	b900f3a0 	str	w0, [x29, #240]
  400824:	52800500 	mov	w0, #0x28                  	// #40
  400828:	b900f7a0 	str	w0, [x29, #244]
  40082c:	a90bffbf 	stp	xzr, xzr, [x29, #184]
  400830:	a90cffbf 	stp	xzr, xzr, [x29, #200]
  400834:	f9006fbf 	str	xzr, [x29, #216]
  400838:	52800140 	mov	w0, #0xa                   	// #10
  40083c:	b900bba0 	str	w0, [x29, #184]
  400840:	528001e0 	mov	w0, #0xf                   	// #15
  400844:	b900bfa0 	str	w0, [x29, #188]
  400848:	52800280 	mov	w0, #0x14                  	// #20
  40084c:	b900c3a0 	str	w0, [x29, #192]
  400850:	52800320 	mov	w0, #0x19                  	// #25
  400854:	b900c7a0 	str	w0, [x29, #196]
  400858:	528003c0 	mov	w0, #0x1e                  	// #30
  40085c:	b900cba0 	str	w0, [x29, #200]
  400860:	52800500 	mov	w0, #0x28                  	// #40
  400864:	b900cfa0 	str	w0, [x29, #204]
  400868:	a9097fbf 	stp	xzr, xzr, [x29, #144]
  40086c:	a90a7fbf 	stp	xzr, xzr, [x29, #160]
  400870:	f9005bbf 	str	xzr, [x29, #176]
  400874:	52800140 	mov	w0, #0xa                   	// #10
  400878:	b90093a0 	str	w0, [x29, #144]
  40087c:	528001e0 	mov	w0, #0xf                   	// #15
  400880:	b90097a0 	str	w0, [x29, #148]
  400884:	52800280 	mov	w0, #0x14                  	// #20
  400888:	b9009ba0 	str	w0, [x29, #152]
  40088c:	52800320 	mov	w0, #0x19                  	// #25
  400890:	b9009fa0 	str	w0, [x29, #156]
  400894:	528003c0 	mov	w0, #0x1e                  	// #30
  400898:	b900a3a0 	str	w0, [x29, #160]
  40089c:	52800500 	mov	w0, #0x28                  	// #40
  4008a0:	b900a7a0 	str	w0, [x29, #164]
  4008a4:	a906ffbf 	stp	xzr, xzr, [x29, #104]
  4008a8:	a907ffbf 	stp	xzr, xzr, [x29, #120]
  4008ac:	f90047bf 	str	xzr, [x29, #136]
  4008b0:	52800140 	mov	w0, #0xa                   	// #10
  4008b4:	b9006ba0 	str	w0, [x29, #104]
  4008b8:	528001e0 	mov	w0, #0xf                   	// #15
  4008bc:	b9006fa0 	str	w0, [x29, #108]
  4008c0:	52800280 	mov	w0, #0x14                  	// #20
  4008c4:	b90073a0 	str	w0, [x29, #112]
  4008c8:	52800320 	mov	w0, #0x19                  	// #25
  4008cc:	b90077a0 	str	w0, [x29, #116]
  4008d0:	528003c0 	mov	w0, #0x1e                  	// #30
  4008d4:	b9007ba0 	str	w0, [x29, #120]
  4008d8:	52800500 	mov	w0, #0x28                  	// #40
  4008dc:	b9007fa0 	str	w0, [x29, #124]
  4008e0:	a9047fbf 	stp	xzr, xzr, [x29, #64]
  4008e4:	a9057fbf 	stp	xzr, xzr, [x29, #80]
  4008e8:	f90033bf 	str	xzr, [x29, #96]
  4008ec:	52800140 	mov	w0, #0xa                   	// #10
  4008f0:	b90043a0 	str	w0, [x29, #64]
  4008f4:	528001e0 	mov	w0, #0xf                   	// #15
  4008f8:	b90047a0 	str	w0, [x29, #68]
  4008fc:	52800280 	mov	w0, #0x14                  	// #20
  400900:	b9004ba0 	str	w0, [x29, #72]
  400904:	52800320 	mov	w0, #0x19                  	// #25
  400908:	b9004fa0 	str	w0, [x29, #76]
  40090c:	528003c0 	mov	w0, #0x1e                  	// #30
  400910:	b90053a0 	str	w0, [x29, #80]
  400914:	52800500 	mov	w0, #0x28                  	// #40
  400918:	b90057a0 	str	w0, [x29, #84]
  40091c:	a901ffbf 	stp	xzr, xzr, [x29, #24]
  400920:	a902ffbf 	stp	xzr, xzr, [x29, #40]
  400924:	f9001fbf 	str	xzr, [x29, #56]
  400928:	52800140 	mov	w0, #0xa                   	// #10
  40092c:	b9001ba0 	str	w0, [x29, #24]
  400930:	528001e0 	mov	w0, #0xf                   	// #15
  400934:	b9001fa0 	str	w0, [x29, #28]
  400938:	52800280 	mov	w0, #0x14                  	// #20
  40093c:	b90023a0 	str	w0, [x29, #32]
  400940:	52800320 	mov	w0, #0x19                  	// #25
  400944:	b90027a0 	str	w0, [x29, #36]
  400948:	528003c0 	mov	w0, #0x1e                  	// #30
  40094c:	b9002ba0 	str	w0, [x29, #40]
  400950:	52800500 	mov	w0, #0x28                  	// #40
  400954:	b9002fa0 	str	w0, [x29, #44]
  400958:	9104c3a0 	add	x0, x29, #0x130
  40095c:	f900afa0 	str	x0, [x29, #344]
  400960:	f940afa0 	ldr	x0, [x29, #344]
  400964:	91001001 	add	x1, x0, #0x4
  400968:	f900afa1 	str	x1, [x29, #344]
  40096c:	b9400001 	ldr	w1, [x0]
  400970:	90000000 	adrp	x0, 400000 <_init-0x480>
  400974:	91334000 	add	x0, x0, #0xcd0
  400978:	97fffede 	bl	4004f0 <printf@plt>
  40097c:	f940afa0 	ldr	x0, [x29, #344]
  400980:	91001001 	add	x1, x0, #0x4
  400984:	f900afa1 	str	x1, [x29, #344]
  400988:	b9400001 	ldr	w1, [x0]
  40098c:	90000000 	adrp	x0, 400000 <_init-0x480>
  400990:	91334000 	add	x0, x0, #0xcd0
  400994:	97fffed7 	bl	4004f0 <printf@plt>
  400998:	f940afa0 	ldr	x0, [x29, #344]
  40099c:	91001001 	add	x1, x0, #0x4
  4009a0:	f900afa1 	str	x1, [x29, #344]
  4009a4:	b9400001 	ldr	w1, [x0]
  4009a8:	90000000 	adrp	x0, 400000 <_init-0x480>
  4009ac:	91334000 	add	x0, x0, #0xcd0
  4009b0:	97fffed0 	bl	4004f0 <printf@plt>
  4009b4:	910423a0 	add	x0, x29, #0x108
  4009b8:	f900afa0 	str	x0, [x29, #344]
  4009bc:	f940afa0 	ldr	x0, [x29, #344]
  4009c0:	91001000 	add	x0, x0, #0x4
  4009c4:	f900afa0 	str	x0, [x29, #344]
  4009c8:	f940afa0 	ldr	x0, [x29, #344]
  4009cc:	b9400001 	ldr	w1, [x0]
  4009d0:	90000000 	adrp	x0, 400000 <_init-0x480>
  4009d4:	91338000 	add	x0, x0, #0xce0
  4009d8:	97fffec6 	bl	4004f0 <printf@plt>
  4009dc:	f940afa0 	ldr	x0, [x29, #344]
  4009e0:	91001000 	add	x0, x0, #0x4
  4009e4:	f900afa0 	str	x0, [x29, #344]
  4009e8:	f940afa0 	ldr	x0, [x29, #344]
  4009ec:	b9400001 	ldr	w1, [x0]
  4009f0:	90000000 	adrp	x0, 400000 <_init-0x480>
  4009f4:	91338000 	add	x0, x0, #0xce0
  4009f8:	97fffebe 	bl	4004f0 <printf@plt>
  4009fc:	f940afa0 	ldr	x0, [x29, #344]
  400a00:	91001000 	add	x0, x0, #0x4
  400a04:	f900afa0 	str	x0, [x29, #344]
  400a08:	f940afa0 	ldr	x0, [x29, #344]
  400a0c:	b9400001 	ldr	w1, [x0]
  400a10:	90000000 	adrp	x0, 400000 <_init-0x480>
  400a14:	91338000 	add	x0, x0, #0xce0
  400a18:	97fffeb6 	bl	4004f0 <printf@plt>
  400a1c:	910383a0 	add	x0, x29, #0xe0
  400a20:	f900afa0 	str	x0, [x29, #344]
  400a24:	f940afa0 	ldr	x0, [x29, #344]
  400a28:	b9400000 	ldr	w0, [x0]
  400a2c:	11000402 	add	w2, w0, #0x1
  400a30:	f940afa1 	ldr	x1, [x29, #344]
  400a34:	b9000022 	str	w2, [x1]
  400a38:	90000001 	adrp	x1, 400000 <_init-0x480>
  400a3c:	9133c022 	add	x2, x1, #0xcf0
  400a40:	2a0003e1 	mov	w1, w0
  400a44:	aa0203e0 	mov	x0, x2
  400a48:	97fffeaa 	bl	4004f0 <printf@plt>
  400a4c:	f940afa0 	ldr	x0, [x29, #344]
  400a50:	b9400000 	ldr	w0, [x0]
  400a54:	11000402 	add	w2, w0, #0x1
  400a58:	f940afa1 	ldr	x1, [x29, #344]
  400a5c:	b9000022 	str	w2, [x1]
  400a60:	90000001 	adrp	x1, 400000 <_init-0x480>
  400a64:	9133c022 	add	x2, x1, #0xcf0
  400a68:	2a0003e1 	mov	w1, w0
  400a6c:	aa0203e0 	mov	x0, x2
  400a70:	97fffea0 	bl	4004f0 <printf@plt>
  400a74:	f940afa0 	ldr	x0, [x29, #344]
  400a78:	b9400000 	ldr	w0, [x0]
  400a7c:	11000402 	add	w2, w0, #0x1
  400a80:	f940afa1 	ldr	x1, [x29, #344]
  400a84:	b9000022 	str	w2, [x1]
  400a88:	90000001 	adrp	x1, 400000 <_init-0x480>
  400a8c:	9133c022 	add	x2, x1, #0xcf0
  400a90:	2a0003e1 	mov	w1, w0
  400a94:	aa0203e0 	mov	x0, x2
  400a98:	97fffe96 	bl	4004f0 <printf@plt>
  400a9c:	9102e3a0 	add	x0, x29, #0xb8
  400aa0:	f900afa0 	str	x0, [x29, #344]
  400aa4:	f940afa0 	ldr	x0, [x29, #344]
  400aa8:	b9400000 	ldr	w0, [x0]
  400aac:	11000401 	add	w1, w0, #0x1
  400ab0:	f940afa0 	ldr	x0, [x29, #344]
  400ab4:	b9000001 	str	w1, [x0]
  400ab8:	f940afa0 	ldr	x0, [x29, #344]
  400abc:	b9400001 	ldr	w1, [x0]
  400ac0:	90000000 	adrp	x0, 400000 <_init-0x480>
  400ac4:	91340000 	add	x0, x0, #0xd00
  400ac8:	97fffe8a 	bl	4004f0 <printf@plt>
  400acc:	f940afa0 	ldr	x0, [x29, #344]
  400ad0:	b9400000 	ldr	w0, [x0]
  400ad4:	11000401 	add	w1, w0, #0x1
  400ad8:	f940afa0 	ldr	x0, [x29, #344]
  400adc:	b9000001 	str	w1, [x0]
  400ae0:	f940afa0 	ldr	x0, [x29, #344]
  400ae4:	b9400001 	ldr	w1, [x0]
  400ae8:	90000000 	adrp	x0, 400000 <_init-0x480>
  400aec:	91340000 	add	x0, x0, #0xd00
  400af0:	97fffe80 	bl	4004f0 <printf@plt>
  400af4:	f940afa0 	ldr	x0, [x29, #344]
  400af8:	b9400000 	ldr	w0, [x0]
  400afc:	11000401 	add	w1, w0, #0x1
  400b00:	f940afa0 	ldr	x0, [x29, #344]
  400b04:	b9000001 	str	w1, [x0]
  400b08:	f940afa0 	ldr	x0, [x29, #344]
  400b0c:	b9400001 	ldr	w1, [x0]
  400b10:	90000000 	adrp	x0, 400000 <_init-0x480>
  400b14:	91340000 	add	x0, x0, #0xd00
  400b18:	97fffe76 	bl	4004f0 <printf@plt>
  400b1c:	910243a0 	add	x0, x29, #0x90
  400b20:	f900afa0 	str	x0, [x29, #344]
  400b24:	f940afa0 	ldr	x0, [x29, #344]
  400b28:	b9400000 	ldr	w0, [x0]
  400b2c:	11000401 	add	w1, w0, #0x1
  400b30:	f940afa0 	ldr	x0, [x29, #344]
  400b34:	b9000001 	str	w1, [x0]
  400b38:	f940afa0 	ldr	x0, [x29, #344]
  400b3c:	b9400001 	ldr	w1, [x0]
  400b40:	90000000 	adrp	x0, 400000 <_init-0x480>
  400b44:	91344000 	add	x0, x0, #0xd10
  400b48:	97fffe6a 	bl	4004f0 <printf@plt>
  400b4c:	f940afa0 	ldr	x0, [x29, #344]
  400b50:	b9400000 	ldr	w0, [x0]
  400b54:	11000401 	add	w1, w0, #0x1
  400b58:	f940afa0 	ldr	x0, [x29, #344]
  400b5c:	b9000001 	str	w1, [x0]
  400b60:	f940afa0 	ldr	x0, [x29, #344]
  400b64:	b9400001 	ldr	w1, [x0]
  400b68:	90000000 	adrp	x0, 400000 <_init-0x480>
  400b6c:	91344000 	add	x0, x0, #0xd10
  400b70:	97fffe60 	bl	4004f0 <printf@plt>
  400b74:	f940afa0 	ldr	x0, [x29, #344]
  400b78:	b9400000 	ldr	w0, [x0]
  400b7c:	11000401 	add	w1, w0, #0x1
  400b80:	f940afa0 	ldr	x0, [x29, #344]
  400b84:	b9000001 	str	w1, [x0]
  400b88:	f940afa0 	ldr	x0, [x29, #344]
  400b8c:	b9400001 	ldr	w1, [x0]
  400b90:	90000000 	adrp	x0, 400000 <_init-0x480>
  400b94:	91344000 	add	x0, x0, #0xd10
  400b98:	97fffe56 	bl	4004f0 <printf@plt>
  400b9c:	97fffe98 	bl	4005fc <point>
  400ba0:	97fffed1 	bl	4006e4 <modify_array>
  400ba4:	97fffeef 	bl	400760 <double_point>
  400ba8:	52800000 	mov	w0, #0x0                   	// #0
  400bac:	a8d67bfd 	ldp	x29, x30, [sp], #352
  400bb0:	d65f03c0 	ret
  400bb4:	00000000 	.inst	0x00000000 ; undefined

0000000000400bb8 <__libc_csu_init>:
  400bb8:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400bbc:	910003fd 	mov	x29, sp
  400bc0:	a901d7f4 	stp	x20, x21, [sp, #24]
  400bc4:	90000094 	adrp	x20, 410000 <__FRAME_END__+0xf2e0>
  400bc8:	90000095 	adrp	x21, 410000 <__FRAME_END__+0xf2e0>
  400bcc:	91374294 	add	x20, x20, #0xdd0
  400bd0:	913722b5 	add	x21, x21, #0xdc8
  400bd4:	a902dff6 	stp	x22, x23, [sp, #40]
  400bd8:	cb150294 	sub	x20, x20, x21
  400bdc:	f9001ff8 	str	x24, [sp, #56]
  400be0:	2a0003f6 	mov	w22, w0
  400be4:	aa0103f7 	mov	x23, x1
  400be8:	9343fe94 	asr	x20, x20, #3
  400bec:	aa0203f8 	mov	x24, x2
  400bf0:	97fffe24 	bl	400480 <_init>
  400bf4:	b4000194 	cbz	x20, 400c24 <__libc_csu_init+0x6c>
  400bf8:	f9000bb3 	str	x19, [x29, #16]
  400bfc:	d2800013 	mov	x19, #0x0                   	// #0
  400c00:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400c04:	aa1803e2 	mov	x2, x24
  400c08:	aa1703e1 	mov	x1, x23
  400c0c:	2a1603e0 	mov	w0, w22
  400c10:	91000673 	add	x19, x19, #0x1
  400c14:	d63f0060 	blr	x3
  400c18:	eb13029f 	cmp	x20, x19
  400c1c:	54ffff21 	b.ne	400c00 <__libc_csu_init+0x48>  // b.any
  400c20:	f9400bb3 	ldr	x19, [x29, #16]
  400c24:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400c28:	a942dff6 	ldp	x22, x23, [sp, #40]
  400c2c:	f9401ff8 	ldr	x24, [sp, #56]
  400c30:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400c34:	d65f03c0 	ret

0000000000400c38 <__libc_csu_fini>:
  400c38:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400c3c <_fini>:
  400c3c:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400c40:	910003fd 	mov	x29, sp
  400c44:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400c48:	d65f03c0 	ret
